1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor package, and particularly relates to a semiconductor device having a Through Silicon VIA electrode structure.
2. Description of the Related Art
Recent versions of information devices such as digital cameras and mobile phones equipped with a camera function embody considerably higher levels of miniaturization, density, and functionality. A wafer-level chip size package (hereinafter referred to as W-CSP) is a known technique for reducing the size of CCD sensors, CMOS sensors, and other imaging elements used in such devices to fit in a chip-scale package.
The W-CSP is a new concept package in which all the assembly steps are completed in a wafer state.
A Through Silicon VIA electrode structure is adopted in the image sensor of a W-CSP structure because reliability can be improved and the device can be made smaller. An electrode that allows the semiconductor device to have signal interchange with the exterior is ordinarily formed on the same surface as the formation surface of the semiconductor elements. In contrast, with Through Silicon VIA electrodes, Through Silicon VIA holes are formed in the thickness direction of the chip from the reverse side of the chip using microfabrication, conductive wiring is formed inside the Through Silicon VIA holes, and the conductive wiring is connected to surface electrodes, whereby signal interchange is made possible from the reverse surface of the chip which is not ordinarily used. Stacking a plurality of chips using a Through Silicon VIA electrode technique and forming signal transmission pathways in the thickness direction of the chip makes it possible to make wiring distances shorter than with conventional wiring. Therefore, packaging density can be dramatically improved and speed and reliability can be increased. Methods for manufacturing CSP having a Through Silicon VIA electrode are described in, e.g., Japanese Laid-open Patent Application Nos. 2006-128171 and 2005-235858.
A CMOS sensor, for example, is an imaging element for reading an electric charge accumulated in a photodiode that has been converted to voltage and amplified in each pixel, and is provided with a photodiode, a cell amplifier, and the like inside a unit cell. A CMOS sensor is composed of a plurality of active elements that constitute a photodiode and a cell amplifier on a semiconductor substrate, and STI (shallow trench isolation) is used for discrete insulation between each active element. The region for forming transistors, diodes, and other active elements on the semiconductor substrate is referred to as an active area, while a region other than the active area is referred to as a non-active area. In other words, STI and other element isolation regions belong to the non-active area. Flattening by CMP (chemical mechanical polishing) is carried out in the step for forming an STI on the semiconductor substrate, and dishing occurs. In dishing, the center portion of the STI is formed into a concave dish-shape by the difference in polishing rates between the oxide film constituting the STI and the nitride film provided as a stopper during polishing when the surface area of the STI region is increased. Difficulties arise in later steps because the flatness of the substrate is detracted when dishing occurs. A technique for preventing dishing involves the formation of a dummy pattern having a plurality of island-shaped dummy sections inside the non-active area, which is the location when dishing occurs. The dummy pattern is formed by leaving the base material of the silicon substrate in island shapes inside the STI region, and is therefore referred to as a dummy active. Dishing can be prevented because the difference between the polishing rates in the CMP step is lessened by the uniform formation of a dummy active in the non-active area (STI region).
In an image sensor having a W-CSP structure, a Through Silicon VIA electrode is generally formed in the non-active area in which active elements are not formed, and a plurality of dummy actives is formed in order to prevent dishing in the non-active area as described above. In other words, a dry etching step for forming Through Silicon VIA holes in the non-active area in which the plurality of dummy actives is formed is included in the steps for manufacturing an image sensor. However, there is a problem in that notches (outwardly expanding depressions in the side wall of the Through Silicon VIA hole) are generated in the sidewall of the Through Silicon VIA holes when Through Silicon VIA holes are formed so as to pass through the non-active area in which the plurality of dummy actives are uniformly disposed.
FIG. 1A is a plan view showing the surface structure of a semiconductor substrate in the Through Silicon VIA electrode formation area in a conventional image sensor. The Through Silicon VIA hole 21 has a substantially cylindrical shape and is formed in the non-active area 100 in which photodiodes, transistors and other active elements are not formed. The non-active area 100 comprises an STI region mainly composed of SiO2. A plurality of island-shaped dummy actives 200 for preventing dishing is uniformed disposed in the non-active area (STI region). The Through Silicon VIA hole 21 is formed so as to pass through the non-active area in which the plurality of dummy actives 200 is arrayed. At this point, dummy actives 200 are present in positions in which the outer edge of the Through Silicon VIA hole 21 passes because the array pitch and the dimensions of the dummy actives 200 are relatively small in comparison with the size of the Through Silicon VIA hole 21.
FIG. 1B is a cross-sectional view along the line 1B-1B in FIG. 1A. An interlayer insulating film 12 is formed on the semiconductor substrate 10. The electrode pad 13 electrically connected to the sensor section is formed in the interlayer insulating film 12. The Through Silicon VIA electrode is formed by forming a Through Silicon VIA hole 21 from the reverse surface of the semiconductor substrate toward the electrode pad 13 by dry etching. Notches 300 are generated in the dry etching process when dummy actives 200 are present in positions through which the outer edge of the Through Silicon VIA hole passes, i.e., when the outer edge of the Through Silicon VIA hole intersects with the dummy actives 200. The notches 300 are depressions formed in the sidewall of the Through Silicon VIA hole 21 in positions at the depth near the boundary between the interlayer insulating film 12 and the semiconductor substrate 10. In FIG. 1A, the locations where notches are generated are indicated by shading. It is apparent from the drawing that the notches 300 are generated only in locations where the outer edge of the Through Silicon VIA hole 21 intersects with the dummy actives 200.
In the step for forming a Through Silicon VIA electrode, a Through Silicon VIA hole 21 is formed, after which a process is carried out to sequentially form plating composed of a barrier metal, a plating seed layer, and electroconductive wiring of the Through Silicon VIA electrode on the inner wall of the Through Silicon VIA hole. Cu is generally used as the plating. However, because Cu is a typical material that constitutes metal contamination in the silicon device and diffuses into the silicon substrate and the interlayer insulating film at lower temperatures, there is a risk of a deterioration of the device performance and reliability, for example, junction leaks and dielectric breakdowns in the interlayer insulating film. For this reason, a barrier metal composed of Ti, Ti/Ni, or the like is formed between the semiconductor substrate and the Cu film that constitutes the electroconductive wiring of the Through Silicon VIA electrode in order to prevent Cu-diffusion into the silicon substrate.
However, it is difficult to form a sufficient barrier metal in the area where notches are generated in the case that notches occur in the sidewall of the Through Silicon VIA hole, and insufficient coverage by the barrier metal is liable to occur in notched area. In this case, Cu could diffuse into the semiconductor substrate in the areas where there is insufficient coverage by the barrier metal, and the device performance and reliability are seriously affected.